(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for arranging staggered bond I/O buffers as linear bond I/O buffers.
(2) Description of the Prior Art
Semiconductor Integrated Circuit (IC) chips or die contain multiple co-functional components that together constitute a complex and extremely densely packed arrangement of electrical components. The layout of the semniconductor die is typically divided into separate functional areas of which the logic functions are one of the major functions on the surface of the IC. With the increased complexity of IC devices, logic functions are contained within complete functional blocks such as a Central Processing Unit (CPU), further supported by a Read Only Memory (ROM) block, clock and timing units, Random Access Memory (RAM) functions and Input/Output (I/O) units. The I/O units can for instance provide an electrical interface between the CPU unit and peripheral devices that are functionally connected to the CPU. The overall layout of the semiconductor die is divided in the highlighted function in order to enable and facilitate the design of the surface area of the substrate on the surface of which these components are created. The logic functions on the surface of the substrate may contain numerous individual logic elements such as gate electrodes or combinations of logic cells to perform specific logic functions.
The completed IC must, with the above highlighted supporting functions such as RAM and ROM functions, be further connected to surrounding circuitry. This interconnection is typically achieved by wire-bonding the IC whereby internal IC functions or functional blocks are connected to at least one bond pad which is used as an electrical interface for I/O signals. The IC is mounted in a plastic or ceramic based package for macro-level interconnection of the IC, the package is provided with I/O pins or contact balls, which are connected to the I/O bond pads of the IC. The I/O pins of the package make contact with higher level device support surfaces such as the surface of a Printed circuit Board (PCB), which in turn may be provided with at least one layer of interconnect traces for purposes of establishing an electrically conductive interconnect network.
Power, such as VDD and VSS voltages, is connected to the IC by means of the bond pads whereby each of these bond pads is connected to a power I/O cell, which in turn is connected to power rings or leads on the surface of the substrate. The power rings supply individual units on the surface of the substrate with the required level of voltage such as VDD or VSS. Power rings are for instance used to supply power to I/O circuitry or to internal logic circuitry. The same functional units can in this manner be provided with ground connections.
It will be appreciated, due to the extreme density and the extreme complexity of the circuitry and functional components that are provided as part of an IC, that connections of power and ground and signal constitute an important aspect of the overall design and layout of the IC. This design is, as always, under severe restrictions of surface area that is required for these interconnections while it is to be expected that various methods, such as staggered I/O connections and linear I/O connections, are applied in order to meet various requirements of design. The invention addresses issues of I/O design. A method is provided whereby staggered I/O connections are converted into linear bond I/O connections, meeting requirements of I/O interconnect of the IC while at the same time reducing the surface area that is required for the needed I/O interconnects.
U.S. Pat. No. 6,214,638 (Banerjee) shows a bond pad layout with staggered positioning.
U.S. Pat. No. 6,057,169 (Singh et al.) reveals a bond pad I/O layout.
U.S. Pat. No. 5,818,114 (Pendse et al.) shows a radially staggered BP layout.
U.S. Pat. No. 5,641,978 (Jassowski) and U.S. Pat. No.6,222,213 (Fujiwara) are related patents.
A principle objective of the invention is to pack a staggered bond pad I/O layout into a linear bond pad I/O layout.
Another objective of the invention is to enable the re-use of circuits and layout of an Integrated Circuit without being affected by bond pad layout.
Yet another objective of the invention is to pack a staggered bond pad I/O layout into a linear bond pad I/O layout without having a negative impact on device performance.
A still further objective of the invention is to provide a method of I/O interconnects that does not require I/O re-design when going from one technology to another technology, making I/O interconnect layout interchangeable between different technologies.
In accordance with the objectives of the invention a new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.